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19-2552; Rev 2; 4/03
KIT ATION EVALU ABLE AVAIL
VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller
General Description Features
o +4.75V to +5.5V or +8V to +28V Input Voltage Range o Up to 60A Output Current o Internal Voltage Regulator for a +12V or +24V Power Bus o Internal 5-Bit DAC VID Control (VRM 9.0 Compliant, 0.8% Accuracy) o Programmable Adaptive Output Voltage Positioning o True Differential Remote Output Sensing o Out-Of-Phase Controllers Reduce Input Capacitance Requirement and Distribute Power Dissipation o Average Current-Mode Control Superior Current Sharing Between Individual Phases and Paralleled Modules Accurate Current Limit Eliminates MOSFET and Inductor Derating o Integrated High-Output-Current Gate Drivers o Selectable Fixed Frequency 250kHz or 500kHz Per Phase (Up to 1MHz for 2 Phases) o External Frequency Synchronization from 125kHz to 600kHz o Internal PLL with Clock Output for Paralleling Multiple DC-DC Converters o Power-Good Output o Phase Failure Detector (Patent Pending) o Overvoltage and Thermal Protection o 44-Pin MQFP or QFN Packages
MAX5037
The MAX5037 dual-phase, PWM controller provides high-output-current capability in a compact package with a minimum number of external components. The MAX5037 utilizes a dual-phase, average current-mode control that enables optimal use of low R DS(ON) MOSFETs, eliminating the need for external heatsinks even when delivering high output currents. Differential sensing enables accurate control of the output voltage, while adaptive voltage positioning provides optimum transient response. An internal regulator enables operation with either +5V or +12V input voltage without the need for additional voltage sources. The high switching frequency, up to 500kHz per phase, and dual-phase operation allow the use of low output inductor values and input capacitor values. This accommodates the use of PC board-embedded planar magnetics achieving superior reliability, current sharing, thermal management, compact size, and low system cost. The MAX5037 also features a clock input (CLKIN) for synchronization to an external clock, and a clock output (CLKOUT) with programmable phase delay (relative to CLKIN) for paralleling multiple phases. The MAX5037 operates over the extended industrial temperature range (-40C to +85C) and is available in 44-pin MQFP or thin QFN packages. Refer to the MAX5038/MAX5041 data sheet for either a fixed output voltage controller or an adjustable output voltage controller in a 28-pin SSOP package.
Applications
Servers and Workstations Point-Of-Load High-Current/High-Density Telecom DC-DC Regulators Networking Systems Large-Memory Arrays RAID Systems High-End Desktop Computers
Ordering Information
PART MAX5037EMH MAX5037ETH TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 44 MQFP 44 Thin QFN
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
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VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller MAX5037
ABSOLUTE MAXIMUM RATINGS
IN to SGND.............................................................-0.3V to +30V BST_ to SGND.............................................. .-0.3V to +35V DH_ to LX_ .................................-0.3V to [(VBST_ - VLX_) + 0.3V] DL_ to PGND ..............................................-0.3V to (VDD + 0.3V) BST_ to LX_ ..............................................................-0.3V to +6V VCC to SGND............................................................-0.3V to +6V VDD to PGND............................................................-0.3V to +6V SGND to PGND .....................................................-0.3V to +0.3V All Other Pins to SGND...............................-0.3V to (VCC + 0.3V) Continuous Power Dissipation (TA = +70C) 44-Pin MQFP (derate 12.7mW/C above +70C)........1013mW 44-Pin QFN (derate 27.0mW/C above +70C) .......2162.2mW Package Thermal Resistance, JC (QFN only) ..................2C/W Operating Temperature Range ...........................-40C to +85C Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = VDD = +5V, circuit of Figure 1, TA = -40C to +85C, unless otherwise noted. Typical specifications are at TA = +25C.) (Note 1)
PARAMETER SYSTEM SPECIFICATIONS 8 Input Voltage Range VIN Short IN and VCC together for 5V input operation EN = VCC or SGND, VID inputs unconnected ILOAD = 52A (26A per phase) VCC falling 4.0 4.75 4 90 4.15 200 VIN = 8V to 28V, ISOURCE = 0 to 80mA RREG = RF = 100k, RIN = 1k, no load (Figure 3) Nominal Output Voltage Accuracy (VID Setting) VIN = VCC = 4.75V to 5.5V, or VIN = 8V to 28V, RREG = RF = 100k, RIN = 1k, no load (Figure 3) IREG_MAX d (VOUT) ICNTR_MAX d (VCNTR) TA = 0C to +85C TA = -40C to +85C Low or high output TA = 0C to +85C TA = -40C to +85C 4.85 5.1 5.30 4.5 28 5.5 6 V SYMBOL CONDITIONS MIN TYP MAX UNITS
Quiescent Supply Current Efficiency STARTUP/INTERNAL REGULATOR VCC Undervoltage Lockout VCC Undervoltage Lockout Hysteresis VCC Output Accuracy
IQ UVLO
mA % V mV V
VOUT/ADAPTIVE VOLTAGE POSITIONING (AVP) -0.8 +0.8 % -1 50 -3 -5 50 -3 -5 1 4 +3 +5 3 +3 +5 +1 A % A %
Maximum REG Loading REG Accuracy (Voltage Positioning) Maximum CNTR Loading Center Voltage Set-Point Accuracy (Note 2) MOSFET DRIVERS Output Driver Impedance Output Driver Peak Source/Sink Current
RON IDH_, IDL_
A
2
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VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller
ELECTRICAL CHARACTERISTICS (continued)
(VCC = VDD = +5V, circuit of Figure 1, TA = -40C to +85C, unless otherwise noted. Typical specifications are at TA = +25C.) (Note 1)
PARAMETER Non-Overlap Time OSCILLATOR AND PLL Switching Frequency PLL Lock Range PLL Locking Time CLKOUT Phase Shift (at fSW = 125kHz) CLKIN Input Pulldown Current CLKIN High Threshold CLKIN Low Threshold CLKIN High Pulse Width PHASE High Threshold PHASE Low Threshold PHASE Input Bias Current CLKOUT Output Low Level CLKOUT Output High Level CURRENT LIMIT Average Current-Limit Threshold Cycle-by-Cycle Current Limit Cycle-by-Cycle Overload Response Time CURRENT-SENSE AMPLIFIER CSP_ to CSN_ Input Resistance Common-Mode Range Input Offset Voltage Amplifier Gain 3dB Bandwidth Transconductance Open-Loop Gain Common-Mode Voltage Range DIFF Output Voltage Input Offset Voltage Amplifier Gain 3dB Bandwidth Minimum Output Current Drive RCS_ VCMR(CS) VOS(CS) AV(CS) f3dB gmca AVOL(CE) VCMR(DIFF) VCM VOS(DIFF) AV(DIFF) f3dB IOUT(DIFF) CDIFF = 20pF 1.0 VSENSE+ = VSENSE- = 0 -1 0.997 1 3 No load -0.3 0.6 +1 1.003 -0.3 -1 18 4 550 50 +1.0 4 +3.6 +1 k V mV V/V MHz S dB V V mV V/V MHz mA VCL VCLPK tR CSP_ to CSN_ CSP_ to CSN_ (Note 4) VCSP_ to VCSN_ = 150mV 45 90 48 112 260 51 130 mV mV ns fSW fPLL tPLL PHASE = VCC 115 85 55 3 2.4 0.8 200 4 1 -50 ISINK = 2mA (Note 3) ISOURCE = 2mA (Note 3) 4.5 +50 100 CLKIN = SGND CLKIN = VCC 238 475 125 200 120 90 60 5 125 95 65 7 A V V ns V V A mV V degrees PHASE = unconnected PHASE = SGND ICLKIN VCLKINH VCLKINL tCLKIN VPHASEH VPHASEL IPHASEBIAS VCLKOUTL VCLKOUTH 250 500 262 525 600 kHz kHz s SYMBOL tNO CONDITIONS CDH_/DL_ = 5nF MIN TYP 60 MAX UNITS ns
MAX5037
CLKOUT
CURRENT-ERROR AMPLIFIER (TRANSCONDUCTANCE AMPLIFIER)
DIFFERENTIAL VOLTAGE AMPLIFIER (DIFF)
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3
VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller MAX5037
ELECTRICAL CHARACTERISTICS (continued)
(VCC = VDD = +5V, circuit of Figure 1, TA = -40C to +85C, unless otherwise noted. Typical specifications are at TA = +25C.) (Note 1)
PARAMETER SENSE+ to SENSE- Input Resistance Open-Loop Gain Unity-Gain Bandwidth EAN Input Bias Current Error-Amp Output Clamping Voltage SYMBOL RVS_ CONDITIONS MIN 50 TYP 100 MAX UNITS k
VOLTAGE-ERROR AMPLIFIER (EAOUT) AVOL(EA) fUGEA IB(EA) CNTR and REG = open, VEAN = 2.0V -100 810 70 3 100 918 dB MHz nA mV
VCLAMP(EA) With respect to VCM
POWER-GOOD, PHASE FAILURE DETECTION, OVERVOLTAGE PROTECTION, AND THERMAL SHUTDOWN PGOOD Trip Level PGOOD Output Low Level PGOOD Output Leakage Current Phase Failure Trip Threshold OVPIN Trip Threshold OVPOUT Source/Sink Current OVPIN Input Resistance Thermal Shutdown Thermal-Shutdown Hysteresis LOGIC INPUTS FOR VID Logic-Input Pullup Resistors Logic-Input Low Voltage Logic-Input High Voltage VID Internal Pullup Voltage EN INPUT EN Input Low Voltage EN Input High Voltage EN Pullup Current VENL VENH IEN 3 4.5 5 5.5 1 V V A RVID VIL VIH VVID All VID_ inputs unconnected 1.7 2.8 2.9 3.2 8 12 20 0.8 k V V V VOV VUV VPGLO IPG VPH OVPTH IOVPOUT ROVPIN TSHDN PGOOD goes low when VOUT is outside of this window ISINK = 4mA PGOOD = VCC PGOOD goes low when CLP_ is higher than VPH Above VID programmed output voltage VOVPOUT = 2.5V +10 15 190 2.0 +13 20 280 150 8 370 +15 +6 -12.5 +8 -10 +10 -8.5 0.20 1 % VO
(VID)
V A V % VO
(VID)
mA k C C
Note 1: Specifications from -40C to 0C are guaranteed by characterization but not production tested. Note 2: CNTR voltage accuracy is defined as the center of the adaptive voltage-positioning window (see Adaptive Voltage Positioning section). Note 3: Guaranteed by design. Not production tested. Note 4: See Peak-Current Comparator section.
4
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VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller
Typical Operating Characteristics
(Circuit of Figure 1, TA = +25C, unless otherwise noted.)
MAX5037
EFFICIENCY vs. OUTPUT CURRENT AND INTERNAL OSCILLATOR FREQUENCY
MAX5037 toc01
EFFICIENCY vs. OUTPUT CURRENT AND INPUT VOLTAGE
MAX5037 toc02
EFFICIENCY vs. OUTPUT CURRENT
90 80 70
MAX5037 toc03
100 90 80 (%) 70 60 50 40
100 90 80 70 VIN = +12V VIN = +5V
100
f = 500kHz f = 250kHz
(%)
(%)
60 50 40 30 20
60 50 40 30 20
VIN = +5V VOUT = +1.8V 0 4 8 12 16 20 24 28 32 36 40 44 48 52 IOUT (A)
10 0
VOUT = +1.8V fSW = 250kHz 0 4 8 12 16 20 24 28 32 36 40 44 48 52 IOUT (A)
10 0
VIN = +24V VOUT = +1.8V fSW = 125kHz 0 4 8 12 16 20 24 28 32 36 40 44 48 52 IOUT (A)
EFFICIENCY vs. OUTPUT CURRENT AND OUTPUT VOLTAGE
MAX5037 toc04
EFFICIENCY vs. OUTPUT CURRENT AND OUTPUT VOLTAGE
MAX5037 toc05
SUPPLY CURRENT vs. FREQUENCY AND INPUT VOLTAGE
12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 ICC (mA)
MAX5037 toc06
100 90 80 70 (%) 60 50 40 30 20 10 0 VIN = +12V fSW = 250kHz VOUT = +1.1V VOUT = +1.5V VOUT = +1.8V
100 90 80 70 (%) 60 50 40 30 20 10 0 VIN = +5V fSW = 500kHz VOUT = +1.1V VOUT = +1.5V VOUT = +1.8V
VIN = +24V
VIN = +12V
VIN = +5V
EXTERNALCLOCK NO DRIVER LOAD
0 4 8 12 16 20 24 28 32 36 40 44 48 52 IOUT (A)
0 4 8 12 16 20 24 28 32 36 40 44 48 52 IOUT (A)
100 150 200 250 300 350 400 450 500 550 600 FREQUENCY (kHz)
SUPPLY CURRENT vs. TEMPERATURE AND FREQUENCY
MAX5037 toc07
SUPPLY CURRENT vs. TEMPERATURE AND FREQUENCY
MAX5037 toc08
SUPPLY CURRENT vs. LOAD CAPACITANCE PER DRIVER
90 80 70 ICC (mA) 60 50 40
MAX5037 toc09
100 90 80 70 ICC (mA) 250kHz
175 600kHz 150 125 500kHz
100
50 40 30 20 10 0 VIN = +12V CDL_ = 22nF CDH_ = 8.2nF -40 -15 10
125kHz
ICC (mA)
60
100 75 50 25 VIN = +5V CDL_ = 22nF CDH_ = 8.2nF -40 -15 10 35 60 85
30 20 10 0 1 3 5 7 9 11 13 15 TEMPERATURE (C) CDRIVER (nF) VIN = +12V fSW = 250kHz
35
60
85
TEMPERATURE (C)
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5
VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller MAX5037
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA = +25C, unless otherwise noted.)
CURRENT-SENSE THRESHOLD vs. OUTPUT VOLTAGE
MAX5037 toc10
OVERVOLTAGE THRESHOLD (PGOOD) vs. INPUT VOLTAGE
MAX5037 toc11
OVERVOLTAGE THRESHOLD (OVPOUT) vs. INPUT VOLTAGE
2.0 1.9 1.8 OVPTH (V) 1.7 1.6 1.5 1.4
MAX5037 toc12
55 54 53 (VCSP_ - VCSN_) (mV) 52
2.0 1.9 1.8 1.7 VOV (V) 1.6 1.5 1.4 1.3 1.2 1.1 1.0 VOUT = +1.1V VOUT = +1.8V
2.1 VOUT = +1.8V
51 50 49 48 47 46 45 1.0 1.1 1.2 1.3 1.4 VOUT (V) 1.5 1.6 1.7 1.8 PHASE 2 PHASE 1
1.3 1.2 1.1
VOUT = +1.1V
4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25 VIN (V)
4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25 VIN (V)
UNDERVOLTAGE THRESHOLD (PGOOD) vs. INPUT VOLTAGE
MAX5037 toc13
OUTPUT VOLTAGE vs. ILOAD AND RCNTR
MAX5037 toc14
OUTPUT VOLTAGE vs. ILOAD AND RCNTR
1.55 1.50 RCNTR = 50k VIN = +12V VID SETTING = +1.4V
MAX5037 toc15 MAX5037 toc18
1.75 1.65 1.55 1.45 VOUT = +1.8V
1.90 1.85 1.80 VOUT (V) RCNTR = 100k 1.75 1.70 RCNTR = 200k 1.65 1.60 VIN = +12V VID SETTING = +1.75V 0 RCNTR = RCNTR = 50k
1.60
VOUT (V)
VUV (V)
1.35 1.25 1.15 1.05 0.95 0.85 0.75 4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25 VIN (V) VOUT = +1.1V
1.45 1.40 1.35 1.30 1.25 1.20 0 5 10 15 20 25 30 35 40 45 50 55 ILOAD (A) RCNTR = 100k RCNTR = 200k RCNTR =
5 10 15 20 25 30 35 40 45 50 55 ILOAD (A)
OUTPUT VOLTAGE vs. OUTPUT CURRENT AND ERROR AMP GAIN (RF / RIN)
MAX5037 toc16
DIFFERENTIAL AMPLIFIER BANDWIDTH
3.5 3.0 PHASE 2.5 GAIN (V/V) 2.0 -90 1.5 1.0 0.5 GAIN -135 -180 -225 -270 0.01 0.1 1 10 FREQUENCY (MHz)
MAX5037 toc17
DIFF OUTPUT ERROR vs. SENSE+ TO SENSE- VOLTAGE
90 45 0 PHASE (deg) ERROR (%) -45 0.200 0.175 0.150 0.125 0.100 0.075 0.050 0.025 0 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 VSENSE (V) VIN = +12V NO DRIVER
1.85
VIN = +12V VOUT = +1.8V
Rf / RIN = 15 Rf / RIN = 12.5
1.80
VOUT (V)
1.75
1.70
Rf / RIN = 7.5 Rf / RIN = 10
1.65
1.60 0 5 10 15 20 25 30 35 40 45 50 55 ILOAD (A)
0
6
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VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA = +25C, unless otherwise noted.)
MAX5037
VCC LOAD REGULATION vs. INPUT VOLTAGE
MAX5037 toc19
VCC LINE REGULATION
5.20 5.15 5.10 VCC (V) VCC (V) 5.05 5.00 4.95 4.90 ICC = 40mA ICC = 0
MAX5037 toc20
VCC LINE REGULATION
5.20 5.15 5.10 5.05 5.00 4.95 4.90 4.85 4.80 4.75 ICC = 80mA 8.0 9.0 10.0 11.0 VIN (V) 12.0 13.0
MAX5037 toc20
5.20 5.15 5.10 5.05 VCC (V) 5.00 4.95 4.90 4.85 DC LOAD 4.80 0 VIN = +8V VIN = +24V VIN = +12V
5.25
5.25
4.85 4.80 4.75 8 10 12 14 16 18 20 22 24 26 28 VIN (V) ICC (mA) 15 30 45 60 75 90 105 120 135 150
DRIVER RISE TIME vs. DRIVER LOAD CAPACITANCE
120 110 100 90 80 70 60 50 40 30 20 10 0 1 6 11 16 21 120 110 100 90 80 70 60 50 40 30 20 10 0 1
MAX5037 toc22
DRIVER FALL TIME vs. DRIVER LOAD CAPACITANCE
MAX5037 toc23
HIGH-SIDE DRIVER (DH_) SINK AND SOURCE CURRENT
MAX5037 toc24
tR (ns)
DL_ DH_
tR (ns)
DL_ DH_
DH_ 1.6A/div
VIN = +12V fSW = 250kHz 26 31 36
VIN = +12V fSW = 250kHz 6 11 16 21 26 31 36
VIN = +12V CDH_ = 22nF 100ns/div
CDRIVER (nF)
CDRIVER (nF)
LOW-SIDE DRIVER (DL_) SINK AND SOURCE CURRENT
MAX5037 toc25
PLL LOCKING TIME 250kHz TO 350kHz AND 350kHz TO 250kHz MAX5037 toc26
CLKOUT 5V/div 350kHz PLLCMP DL_ 1.6A/div 200mV/div
PLL LOCKING TIME 250kHz TO 500kHz AND 500kHz TO 250kHz MAX5037 toc27
CLKOUT 5V/div
250kHz PLLCMP 200mV/div 250kHz VIN = +12V NO LOAD 0 100s/div
500kHz
0 VIN = +12V CDL_ = 22nF 100ns/div
VIN = +12V NO LOAD 100s/div
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7
VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller MAX5037
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA = +25C, unless otherwise noted.)
PLL LOCKING TIME 250kHz TO 150kHz AND 150kHz TO 250kHz MAX5037 toc28
CLKOUT 5V/div
HIGH-SIDE DRIVER (DH_) RISE TIME
MAX5037 toc29
HIGH-SIDE DRIVER (DH_) FALL TIME
MAX5037 toc30
250kHz PLLCMP 200mV/div 150kHz 0 VIN = +12V NO LOAD 100s/div VIN = +12V CDH_ = 22nF 40ns/div
DH_ 2V/div
DH_ 2V/div
VIN = +12V CDH_ = 22nF 40ns/div
LOW-SIDE DRIVER (DL_) RISE TIME
MAX5037 toc31
LOW-SIDE DRIVER (DL_) FALL TIME
MAX5037 toc32
OUTPUT RIPPLE
MAX5037 toc33
DL_ 2V/div
DL_ 2V/div VOUT (AC-COUPLED) 10mV/div
VIN = +12V CDL_ = 22nF 40ns/div
VIN = +12V CDL_ = 22nF 40ns/div
VIN = +12V VOUT = +1.75V IOUT = 52A 500ns/div
INPUT STARTUP RESPONSE
MAX5037 toc34
ENABLE STARTUP RESPONSE
MAX5037 toc35
LOAD-TRANSIENT RESPONSE
MAX5037 toc36
VPGOOD 1V/div
VPGOOD 1V/div
VOUT 1V/div
VOUT 1V/div
VOUT 50mV/div
VIN 5V/div VIN = +12V VOUT = +1.75V IOUT = 52A 2ms/div 1ms/div VIN = +12V VOUT = +1.75V IOUT = 52A
VEN 2V/div
VIN = +12V VOUT = +1.75V ISTEP = 8A TO 52A tRISE = 1s 40s/div
8
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VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller
Pin Description
PIN 1-4, 44 NAME VID3-VID0, VID4 SGND FUNCTION DAC Code Inputs. VID0 is the LSB and VID4 is the MSB for the internal 5-bit DAC (Table 1). Connect to SGND for logic low or leave open circuit for logic high. These inputs have 12k internal pullup resistors to an internal 3V regulator. Signal Ground. Ground connection for the internal circuitry. QFN package exposed pad connected to SGND. Overvoltage Protection Circuit Input. Connect DIFF to OVPIN. When OVPIN exceeds +13% above the VID programmed output voltage, OVPOUT latches DH_ low and DL_ high. Toggle EN low to high or recycle the power to reset the latch.
MAX5037
5, 20, 35
6 7, 43 8
OVPIN
CLP1, CLP2 Current-Error Amplifier Output. Compensate the current loop by connecting an R-C network to ground. OVPOUT Overvoltage Protection Output. Use the OVPOUT active-high, push-pull output to trigger a safety device such as an SCR. Power-Good Output. The open-drain, active-low PGOOD output goes low when the VID programmed output voltage falls out of regulation or a phase failure is detected. The power-good window comparator thresholds are +8% and -10% of the VID programmed output voltage. Forcing EN low also forces PGOOD low. Differential Output Voltage-Sensing Positive Input. Used to sense a remote load. Connect SENSE+ to VOUT+ at the load. The device regulates the difference between SENSE+ and SENSE- according to the programmed VID code and adaptive voltage positioning. Differential Output Voltage-Sensing Negative Input. Used to sense a remote load. Connect SENSE- to VOUT- or PGND at the load. Differential Remote-Sense Amplifier Output. DIFF is the output of a precision unity-gain amplifier. Voltage-Error Amplifier Inverting Input. Receives the output of the differential remote-sense amplifier. Referenced to SGND. Voltage-Error Amplifier Output. Connect to an external, gain-setting feedback resistor. The error amplifier gain determines the output voltage load regulation for adaptive voltage positioning. REG Input. A resistor on REG applies the same voltage-positioning window at different VRM voltage settings. For a no-load output voltage (VCORE) equal to VID, set RREG = RF, where the RF is the feedback resistor of the voltage-error amplifier. VREG internally regulates to the programmed VID output voltage. Current-Sense Differential Amplifier Positive Input. Senses the inductor current. The differential voltage between CSP_ and CSN_ is amplified internally by the current-sense amplifier gain of 18. Current-Sense Differential Amplifier Negative Input. Senses the inductor current. Adaptive Voltage Center Position Input. Connect a resistor between CNTR and SGND to program the center of the adaptive VOUT position. VCNTR regulates to +1.22V. Output Enable. A logic low shuts down the power drivers. EN has an internal 5A pullup current. No Connection. Not internally connected. Boost Flying-Capacitor Connection. Reservoir capacitor connection for the high-side FET driver supply. Connect 0.47F ceramic capacitors between BST_ and LX_. High-Side Gate-Driver Output. Drives the gate of the high-side MOSFET.
9
PGOOD
10
SENSE+
11 12 13 14
SENSEDIFF EAN EAOUT
15
REG
16, 39 17, 40 18 19 21, 33, 37 22, 34 23, 32
CSP1, CSP2 CSN1, CSN2 CNTR EN N.C. BST1, BST2 DH1, DH2
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9
VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller MAX5037
Pin Description (continued)
PIN 24, 31 25, 30 26 NAME LX1, LX2 DL1, DL2 VDD FUNCTION Inductor Connection. Source connection for the high-side MOSFETs. Also serves as the return terminal for the high-side driver. Low-Side Gate-Driver Output. Synchronous MOSFET gate drivers for the two phases. Supply Voltage for Low-Side and High-Side Drivers. VCC powers VDD. Connect a parallel combination of 0.1F and 1F ceramic capacitors to PGND and a 1 resistor to VCC to filter out the high peak currents of the driver from the internal circuitry. Internal 5V Regulator Output. VCC is derived internally from the IN voltage. Bypass to SGND with 4.7F and 0.1F ceramic capacitors. Supply Voltage Connection. Connect IN to VCC for a 5V system. Power Ground. Connect PGND, low-side synchronous MOSFET's source, and VDD bypass capacitor returns together. Oscillator Output. CLKOUT is phase shifted from CLKIN by the amount specified by PHASE. Use CLKOUT to parallel additional MAX5037s. CMOS Logic Clock Input. Drive the internal oscillator with a frequency range between 125kHz and 600kHz. The PWM frequency defaults to the internal oscillator if CLKIN is connected to VCC or SGND. Connect CLKIN to SGND to set the internal oscillator to 250kHz or connect to VCC to set the internal oscillator to 500kHz. CLKIN has an internal 5A pulldown current. Phase Shift Setting Input. Drive PHASE high for 120, leave PHASE unconnected for 90, and force PHASE low for 60 of phase shift between the rising edges of CLKOUT and CLKIN/DH1. External Loop-Compensation Input. Connect compensation network for the phase-locked loop (see Phase-Locked Loop section).
27 28 29 36
VCC IN PGND CLKOUT
38
CLKIN
41 42
PHASE PLLCMP
10
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VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller
Functional Diagram
EN
MAX5037
IN VCC
+5V LDO REGULATOR TO INTERNAL CIRCUITS
UVLO POR TEMP SENSOR
VDD CSP1 CSN1 CLP1 SGND CSP1 CSN1 CLP1 CLK PHASE 1 DRV_VCC SHDN BST1 DH1 LX1 DL1
MAX5037
GMIN CLKIN PHASELOCKED LOOP PGND RAMP1
CLKOUT PLLCMP DIFF PGOOD SENSEDIFF AMP SENSE+ CLP2 CNTR REG ADAPTIVE VOLTAGE POSITIONING 13% OF DAC_OUT DAC_OUT CLP1 +0.6V DIFF POWERGOOD GENERATOR N RAMP GENERATOR
PGND
EAOUT EAN ERROR AMP
OVP COMP
OVPOUT
VID0 VID1 VID2 VID3 VID4 RAMP2 OVPIN CLP2 CSN2 CSP2 GMIN CLP2 CSN2 CSP2 PHASE 2 ROM VOLTAGEPOSITIONING DAC
DAC_OUT DRV_VCC CLK PGND DH2 LX2 DL2 BST2 SHDN
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11
VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller MAX5037
Detailed Description
The MAX5037 (Figures 1 and 2) average current-mode PWM controller drives two out-of-phase buck converter channels. Average current-mode control improves current sharing between the channels while minimizing component derating and size. Parallel multiple MAX5037 regulators to increase the output current capacity. For maximum ripple rejection at the input, set the phase shift between phases to 90 for two paralleled converters, or 60 for three paralleled converters. Paralleling the MAX5037s improves design flexibility in applications requiring upgrades (higher load). The programmable output voltage utilizes VID codes compliant with Intel's VRM 9.0 specifications.
VIN = +5V C1, C2
VCC VCC R13 C31 C32 R4 IN
C42 VIN 42 38 CLKIN 28 IN 11 10 17 16 DH1 23 24 25 Q2 D1 C12 Q1 L1 R1 C3-C7 5 x 22F
19 EN 44 1 DAC INPUTS 2 3 4 8 C43 R12 VID4
PLLCMP
SENSE- SENSE+ CSN1 CSP1
LX1 VID3 DL1 VID2 VID1 VID0 OVPOUT VDD
VIN
BST1 VCC
22 27
D3
IN VOUT = +1.1V TO +1.85V AT 52A C16-C25 LOAD C26-C30, C37
C41 R3 28 C39 C40 D4
C38
C14, C15
MAX5037
6 R7 12 13 R8 14 OVPIN
VIN DIFF EAN DH2 EAOUT LX2 32 31 30 C13 D2 C8-C11 Q3 L2 R2
R9
15
DL2 REG
Q4
R10
18
CNTR CLP1 7 CLP2 43 PGND 29 SGND PHASE 5, 20, 35 41 PGOOD 9 CSN2 CSP2 40 39 BST2
34
R6 C36 C35
R5 C34 C33 VCC PGOOD
R11
*SEE TABLE 2 FOR COMPONENT VALUES.
Figure 1. Typical VRM Application Circuit, VIN = +5V 12 ______________________________________________________________________________________
VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller
Dual-phase converters with an out-of-phase locking arrangement reduce the input and output capacitor ripple current, effectively multiplying the switching frequency by the number of phases. Each phase of the MAX5037 consists of an inner average current loop controlled by a common outer-loop voltage-error amplifier that corrects the output voltage errors. The MAX5037 utilizes a single controlling voltage-error amplifier and average current mode to force the phase currents to be equal.
MAX5037
VIN = +8V TO +28V C1, C2 2 x 47F R13 2.2
VCC VCC C31 C32 R4
C42 0.1F
VIN C3-C7 5 x 22F DH1 23 24 25 Q2 D1 Q1 L1 0.6H C12 0.47F R1 1.35m
19 EN 44 1 DAC INPUTS 2 3 4 8 C43 R12 VID4
42 PLLCMP
38 CLKIN
28 IN
11 10 17 16 SENSE- SENSE+ CSN1 CSP1
LX1 VID3 DL1 VID2 VID1 VID0 OVPOUT VDD
VIN
BST1 VCC
22 27 C41 0.1F
D3 VOUT = +1.1V TO +1.85V AT 52A LOAD C16-C25 2 x 270F
R3 28 C39 1F VIN
C38 4.7F D4
C14, C15 2 x 100F
MAX5037
6 R7 12 13 R8 14 OVPIN DIFF EAN DH2 EAOUT LX2 R9 15 DL2 REG
C40 0.1F
32 31 30
Q3
C8-C11 4 x 22F L2 0.6H C13 0.47F D2 R2 1.35m
C26-C30, C37 6 x 10F
Q4
R10
18
CNTR CLP1 7 CLP2 43 PGND 29 SGND PHASE 5, 20, 35 41 PGOOD 9 CSN2 CSP2 40 39 BST2
34
R6 C36 C35
R5 C34 C33 VCC PGOOD
R11
NOTE: TABLE 2 FOR COMPONENT VALUES.
Figure 2. Typical VRM Application Circuit, VIN = +8V to +28V ______________________________________________________________________________________ 13
VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller MAX5037
VIN, VCC, and VDD
The MAX5037 accepts a wide input voltage range of +4.75V to +5.5V or +8V to +28V. All internal control circuitry operates from an internally regulated nominal voltage of 5V. For input voltages of +8V or greater, the internal VCC regulator steps the voltage down to +5V. The VCC output voltage regulates to 5V while sourcing up to 80mA. Bypass VCC to SGND with 4.7F and 0.1F low-ESR ceramic capacitors for high-frequency noise rejection and stable operation (Figure 1). VCC powers all internal circuitry. VDD is derived externally from VCC and provides power to the high-side and low-side MOSFET drivers. VDD is internally connected to the power source of the low-side MOSFET drivers. Use VDD to charge the boost capacitors that provide power to the high-side MOSFET drivers. Connect the VCC regulator output to VDD through an R-C lowpass filter. Use a 1 (R3) resistor and a parallel combination of 1F and 0.1F ceramic capacitors to filter out the high peak currents of the MOSFET drivers from the sensitive internal circuitry. Calculate power dissipation in the MAX5037 as a product of the input voltage and the total VCC regulator output current (ICC). ICC includes quiescent current (IQ) and gate drive current (IDD): (1) PD = VIN x ICC ICC = IQ + fSW x (QG1 + QG2 + QG3 + QG4) (2) where, Q G1, Q G2, Q G3, and Q G4 are the total gate charge of the low-side and high-side external MOSFETs, IQ is 4mA (typ), and fSW is the switching frequency of each individual phase. For applications utilizing a +5V input voltage, disable the VCC regulator by connecting IN and VCC together. The compensation network at the current-error amplifier, CLP1 and CLP2, provides an inherent soft-start to the VRM power supply. It includes a parallel combination of capacitors (C34, C36) and resistors (R5, R6) in series with other capacitors (C33, C35) (see Figure 1). The voltage at CLP_ limits the maximum current available to charge output capacitors. The capacitor on CLP_ in conjunction with the finite output-drive current of the current-error amplifier yields a finite rise time for the output current and thus the output voltage.
Internal Oscillator
The internal oscillator generates the 180 out-of-phase clock signals required by the pulse-width modulation (PWM) circuits. The oscillator also generates the 2VP-P voltage ramp signals necessary for the PWM comparators. Connect CLKIN to SGND to set the internal oscillator frequency to 250kHz or connect CLKIN to VCC to set the internal oscillator to 500kHz. CLKIN is a CMOS logic clock for the phase-locked loop (PLL). When driven externally, the internal oscillator locks to the signal at CLKIN. A rising edge at CLKIN starts the ON cycle of the PWM. Ensure that the external clock pulse width is at least 200ns. CLKOUT provides a phase-shifted output with respect to the rising edge of the signal at CLKIN. PHASE sets the amount of phase shift at CLKOUT. Connect PHASE to VCC for 120 of phase shift, leave PHASE unconnected for 90 of phase shift, or connect PHASE to SGND for 60 of phase shift with respect to CLKIN. The MAX5037 requires compensation on PLLCMP even when operating from the internal oscillator. The device requires an active phase-locked loop in order to generate the proper clock signal required for PWM operation.
Undervoltage Lockout (UVLO)/ Power-On Reset (POR)/Soft-Start
The MAX5037 includes an undervoltage lockout with hysteresis and a power-on reset circuit for converter turn-on and monotonic rise of the output voltage. The UVLO circuit monitors the VCC regulator output while actively holding down the power-good (PGOOD) output. The UVLO threshold is internally set between +4.0V and +4.5V with a 200mV hysteresis. Hysteresis at UVLO eliminates "chattering" during startup. Most of the internal circuitry, including the oscillator, turns on when the input voltage reaches +4V. The MAX5037 draws up to 4mA of current before the input voltage reaches the UVLO threshold. The power-on reset clears the overvoltage protection (OVP) fault latch at the UVLO threshold to avoid unintentional OVP latching.
Control Loop
The MAX5037 uses an average current-mode control scheme to regulate the output voltage (Figure 3). The main control loop consists of an inner current loop and an outer voltage loop. The inner loop controls the output currents (IPHASE1 and IPHASE2), while the outer loop controls the output voltage. The inner current loop absorbs the inductor pole reducing the order of the outer voltage loop to that of a single-pole system.
14
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VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller
The current loop consists of a current-sense resistor, RS (an RC lowpass filter in the case of lossless inductor current sensing), a current-sense amplifier (CA_), a current-error amplifier (CEA_), an oscillator providing the carrier ramp, and a PWM comparator (CPWM_). The precision CA_ amplifies the sense voltage across RS by a factor of 18. The inverting input to the CEA_ senses the output of the CA_. The output of the CEA_ is the difference between the voltage-error amplifier output (EAOUT) and the gained-up voltage from the CA_. The RC compensation network connected to CLP1 and CLP2 provides external frequency compensation for the respective CEA_. The start of every clock cycle enables the high-side drivers and initiates a PWM ON cycle. Comparator CPWM_ compares the output voltage from the CEA_ with a 0 to 2V ramp from the oscillator. The PWM ON cycle terminates when the ramp voltage exceeds the error voltage. The outer voltage control loop consists of the differential amplifier (DIFF AMP), adaptive voltage-positioning (AVP) block, digital-to-analog converter (DAC), and voltage-error amplifier (VEA). The unity-gain differential amplifier provides true differential remote sensing of the output voltage. The differential amplifier output and the AVP connect to the inverting input (EAN) of the VEA. The noninverting input of VEA is internally connected to the DAC output. The VEA controls the two inner current loops (Figure 3). Use a resistive feedback network to set the gain of the VEA as required by the adaptive voltage-positioning circuit.
MAX5037
RCF
CCF
CSN1
CSP1
CLP1
CCFF
MAX5037
AVP RF* SENSE+ DIFF AMP SENSERIN* VEA
CA1
VIN
CEA1 CPWM1
IPHASE1 DRIVE 1 RS
VOUT VIN CEA2 CPWM2 COUT LOAD
DAC
DRIVE 2
IPHASE2
RS
CA2
CSN2
CSP2
CLP2
RCF
CCF
*RF AND RIN ARE EXTERNAL TO MAX5037 (RF = R8, RIN = R7, FIGURES 1 AND 2)
CCCF
Figure 3. MAX5037 Control Loop ______________________________________________________________________________________ 15
VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller MAX5037
Current-Sense Amplifier The differential current-sense amplifier (CA_) provides a DC gain of 18. The maximum input offset voltage of the current-sense amplifier is 1mV and the common-mode voltage range is -0.3V to +3.6V. The current-sense amplifier senses the voltage across a current-sense resistor. Peak-Current Comparator The peak-current comparator provides a path for fast cycle-by-cycle current limit during extreme fault conditions such as an output inductor malfunction (Figure 4). Note that the average current-limit threshold of 48mV still limits the output current during short-circuit conditions. So to prevent inductor saturation, select an output inductor with a saturation current specification greater than the average current limit. Proper inductor selection ensures that only extreme conditions trip the peak-current comparator, such as a cracked output inductor. The 112mV voltage threshold for triggering the peak-current limit is twice the full-scale average current-limit voltage threshold. The peak-current comparator has a delay of only 260ns. Current-Error Amplifier Each phase of the MAX5037 has a dedicated transconductance current-error amplifier (CEA_) with a typical gm of 550S and 320A output sink and source current capability. The CEA_ outputs, CLP1 and CLP2, serve as the inverting input to the PWM comparator. CLP1 and CLP2 are externally accessible to provide frequency compensation for the inner current loops (Figure 3). Compensate CEA_ such that the inductor current down slope, which becomes the up slope to the inverting input of the PWM comparator, is less than the slope of the internally generated voltage ramp (see the Compensation section). PWM Comparator and R-S Flip-Flop The PWM comparator (CPWM) sets the duty cycle for each cycle by comparing the current-error amplifier output to a 2VP-P ramp. At the start of each clock cycle, an R-S flip-flop resets and the high-side driver (DH_) turns on. The comparator sets the flip-flop as soon as the ramp voltage exceeds the CLP_ voltage, thus terminating the ON cycle (Figure 4). Differential Amplifier The unity-gain differential amplifier (DIFF AMP) facilitates the output voltage remote sensing at the load (Figure 3). It provides true differential output voltage sensing while rejecting the common-mode voltage errors due to high-current ground paths. Sensing the output voltage directly at the load provides accurate load voltage sensing in high-current environments. The VEA provides the difference between the differential amplifier output (DIFF) and the desired VID programmed output voltage. The differential amplifier has a unity-gain bandwidth of 3MHz. The difference between SENSE+ and SENSE- regulates to the programmed VID output voltage. Connect SENSE+ to an external resistor-divider network at the output voltage to use the MAX5037 for output voltages higher than those allowed by the VID codes.
DRV_VCC
PEAK CURRENT COMPARATOR 112mV CLP_ CSP_ CSN_ GMIN RAMP 2 x fS (V/s) CLK R Q LX_ DL_ AV = 18 Gm = 500S PWM COMPARATOR S
BST_ Q DH_
SHDN
PGND
Figure 4. Phase Circuit (Phase 1/Phase 2) 16 ______________________________________________________________________________________
VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller
Voltage-Error Amplifier The VEA sets the gain of the voltage control loop. The VEA determines the error between the differential amplifier output and the reference voltage generated from the DAC. The VEA output clamps to 0.9V relative to VCM (0.6V), thus limiting the average maximum current from individual phases. The maximum average current-limit threshold for each phase is equal to the maximum clamp voltage of the VEA divided by the gain (18) of the current-sense amplifier. This results in accurate settings for the average maximum current for each phase. Set the VEA gain using RF and RIN for the amount of output voltage positioning required within the rated current range as discussed in the Adaptive Voltage Positioning section (Figure 3). Set the voltage-positioning window (VOUT) using the resistive feedback of the VEA. See the Adaptive Voltage-Positioning Design Procedure section and use the following equation to calculate the voltage-positioning window: (3) VOUT = IOUT x RIN / (2 x GC x RF ) GC = 0.05 RS (4)
MAX5037
Adaptive Voltage Positioning
Powering new generation processors requires new techniques to reduce cost, size, and power dissipation. Voltage positioning reduces the total number of output capacitors to meet a given transient response requirement. Setting the no-load output voltage slightly higher than the output voltage during nominally loaded conditions allows a larger downward voltage excursion when the output current suddenly increases. Regulating at a lower output voltage under a heavy load allows a larger upward voltage excursion when the output current suddenly decreases. A larger allowed voltage step excursion reduces the required number of output capacitors or allows for the use of higher ESR capacitors. Voltage positioning and the ability to operate with the multiple reference voltages may require the output to regulate away from a center value. Define the center value as the voltage where the output equals the VID reference voltage at one half the maximum output current (Figure 5).
where RIN and RF are the input and feedback resistors of the VEA, GC is the current-loop gain, and RS is the current-sense resistor or, if using lossless inductor current sensing, the DC resistance of the inductor. The voltage at CNTR (VCNTR) regulates to 1.2V (Figure 6). The current set by the resistor RCNTR is mirrored at the inverting input of the VEA, centering the output voltage-positioning window on the VID programmed output voltage. Set the center of the output voltage with a resistor from CNTR to SGND in the following manner: RCNTR = VCNTR x RIN RIN IOUT + (VOUT - VID) 2RFGC
(5)
where VOUT is a required value of output voltage at the corresponding IOUT. IOUT can be any value from no load to full load.
VCC
VCC
1X
1X
+1.2V
VCNTR + VOUT/2 VCNTR VCNTR - VOUT/2
EAN CNTR 1X
VOLTAGE-POSITIONING WINDOW
DAC_OUT
1X
NO LOAD
1/2 LOAD LOAD (A)
FULL LOAD
REG
Figure 5. Defining the Voltage-Positioning Window
Figure 6. Adaptive Voltage-Positioning Circuit 17
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VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller
Applying the voltage-positioning window at different VRM voltage settings requires that RREG = RF. The voltage on REG internally regulates to the programmed VID output voltage. Choose RREG to limit the current at REG to 50A. For example, for a VID setting of 1.85V, calculate the minimum allowed R REG as R REG = 1.85V/50A = 37k. To use larger values of RREG while maintaining the required gain of the VEA, use larger values for RIN. In the case of a VID voltage setting equal to VCOREMAX at IOUT = 0 (no load), RCNTR = from the above equation (Figure 7). For systems requiring VCOREMAX as an absolute maximum voltage when IOUT = 0 (no load), calculate RREG using following the equation: RIN x RF RREG = V RIN + RF 1 - COREMAX VID
MAX5037
The available DAC codes and resulting output voltages (Table 1) comply with Intel's VRM 9.0 specification. Internal pullup resistors connect the VID inputs to a nominal internal 3V supply. Force the VID inputs below 0.8V for logic low or leave unconnected for logic high. Output voltage accuracy with respect to the programmed VID voltage is 0.8% over the -40C to +85C temperature range.
Table 1. Output Voltage vs. DAC Codes
VID INPUTS (0 = CONNECTED TO SGND, 1 = OPEN CIRCUIT) VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 OUTPUT VOLTAGE (V) VOUT Output Off 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 1.425 1.450 1.475 1.500 1.525 1.550 1.575 1.600 1.625 1.650 1.675 1.700 1.725 1.750 1.775 1.800 1.825 1.850
(6)
DAC Inputs (VID0-VID4)
The DAC programs the output voltage. The DAC typically receives a digital code, alternatively, the VID inputs are hard-wired to SGND or left open-circuit. VID0-VID4 logic can be changed while the MAX5037 is active, initiating a transition to a new output voltage level. Change VID0-VID4 together, avoiding greater than 1s skew between bits. Otherwise, incorrect DAC readings may cause a partial transition to the wrong voltage level followed by the intended transition to the correct voltage level, lengthening the overall transition time. For any low-going VID step of 100mV or more, the OVP can trip simply because the OVP trip reference changes instantaneously with the VID code, but the converter output does not follow immediately. The converter output drops at a rate depending on the output capacitor, inductor load, and the closed-loop bandwidth of the converter. Do not exceed a maximum VID step size of 75mV.
VOLTAGE-POSITIONING WINDOW
VCOREMAX VID VCOREMAX - VOUT/2 VCOREMAX - VOUT/2
NO LOAD
1/2 LOAD LOAD (A)
FULL LOAD
Figure 7. Limiting the Voltage-Positioning Window 18
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VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller
Phase-Locked Loop: Operation and Compensation
The phase-locked loop (PLL) synchronizes the internal oscillator to the external frequency source when driving CLKIN. Connecting CLKIN to VCC or SGND forces the PWM frequency to default to the internal oscillator frequency of 500kHz or 250kHz, respectively. The PLL uses a conventional architecture consisting of a phase detector and a charge pump capable of providing 20A of output current. Connect an external series combination capacitor (C31) and resistor (R4) and a parallel capacitor (C32) from PLLCMP to SGND to provide frequency compensation for the PLL (Figure 1). The pole-zero pair compensation provides a zero at fZ = 1 / [R4 x (C31 + C32)] and a pole at fP = 1 / (R4 x C32). Use the following typical values for compensating the PLL: R4 = 7.5k, C31 = 4.7nF, C32 = 470pF. When changing the PLL frequency, expect a finite locking time of approximately 200s. The MAX5037 requires compensation on PLLCMP even when operating from the internal oscillator. The device requires an active-phase-locked loop in order to generate the proper internally shifted clock available at CLKOUT.
Protection
The MAX5037 includes output overvoltage protection (OVP), undervoltage protection (UVP), phase failure, and overload protection to prevent damage to the powered electronic circuits. Overvoltage Protection (OVP) The OVP comparator compares the OVPIN input to the overvoltage threshold. The overvoltage threshold is typically +13% above the programmed VID output voltage. A detected overvoltage event latches the comparator output forcing the power stage into the OVP state. In the OVP state, the high-side MOSFETs turn off and the low-side MOSFETs latch on. Use the OVPOUT highcurrent-output driver to turn on an external crowbar SCR. When the crowbar SCR turns on, a fuse must blow or the source current for the MAX5037 regulator must be limited to prevent further damage to the external circuitry. Connect the SCR close to the input source and after the fuse. Use an SCR large enough to handle the peak I2t energy due to the input and output capacitors discharging and the current sourced by the power source output. Connect DIFF to OVPIN for differential output sensing and overvoltage protection. Add an RC delay to reduce the sensitivity of overvoltage circuit and avoid nuisance tripping of the converter (Figure 8). For any low-going VID step of 75mV or more, the OVP can trip because the OVP trip reference changes instantaneously with the VID code, but the converter output does not follow immediately. The converter output drops at a rate depending on the output capacitor, inductor load, and the closed-loop bandwidth of the converter.
MAX5037
MOSFET Gate Drivers (DH_, DL_)
The high-side (DH_) and low-side (DL_) drivers drive the gates of external N-channel MOSFETs (Figure 1). The drivers' high-peak sink and source current capability provides ample drive for the fast rise and fall times of the switching MOSFETs. Faster rise and fall times result in reduced cross-conduction losses. For modern CPU applications where the duty cycle is less than 50%, choose high-side MOSFETs (Q1 and Q3) with a moderate RDS(ON) and very low gate charge. Choose low-side MOSFETs (Q2 and Q4) with very low RDS(ON) and moderate gate charge. The driver block also includes a logic circuit that provides an adaptive non-overlap time to prevent shootthrough currents during transition. The typical non-overlap time is 60ns between the high-side and low-side MOSFETs.
0.1F OVPIN 1k
BST_
VDD powers the low- and high-side MOSFET drivers. The high-side drivers derive their power through a bootstrap capacitor and VDD supplies power internally to the low-side drivers. Connect a 0.47F low-ESR ceramic capacitor between BST_ and LX_. Bypass VDD to PGND with 1F and 0.1F low-ESR ceramic capacitors. Reduce the PC board area formed by these capacitors, the rectifier diodes between VDD and the boost capacitor, the MAX5037, and the switching MOSFETs.
MAX5037
DIFF RIN EAN
RF EAOUT
Figure 8. OVP Input Delay ______________________________________________________________________________________ 19
VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller MAX5037
Power-Good Generator (PGOOD) The PGOOD output is high if all of the following conditions are met (Figure 9): 1) The output is within 90% to 108% of the programmed output voltage. 2) Both phases are providing current. 3) EN is HIGH. A window comparator compares the differential amplifier output (DIFF) against 1.08 times the programmed VID output voltage for overvoltage and 0.90 times the programmed VID output voltage for undervoltage monitoring. The phase failure comparator detects a phase failure by comparing the current-error amplifier output (CLP_) with a 2.0V reference. Use a 10k pullup resistor from PGOOD to a voltage source less than or equal to VCC. An output voltage outside the comparator window or a phase failure condition forces the open-drain output low. The open-drain MOSFET sinks 4mA of current while maintaining less than 0.2V at the PGOOD output. Phase Failure Detector Output current contributions from the two phases are within 10% of each other. Proper current sharing reduces the necessity to overcompensate the external components. However, an undetected failure of one phase driver causes the other phase driver to run continuously as it tries to provide the entire current requirement to the load. Eventually, the stressed operational phase driver fails. During normal operating conditions, the voltage level on CLP_ is within the peak-to-peak voltage levels of the PWM ramp. If one of the phases fails, the control loop raises the CLP_ voltage above its operating range. To determine a phase failure, the phase failure detection circuit (Figure 9) monitors the output of the current amplifiers (CLP1 and CLP2) and compares them to a 2.0V reference. If the voltage levels on CLP1 or CLP2 are above the reference level for more than 1250 clock cycles, the phase failure circuit forces PGOOD low.
Parallel Operation
For applications requiring large output current, parallel up to three MAX5037s (six phases) to triple the available output current. The paralleled converters operating at the same switching frequency but different phases keep the capacitor ripple RMS currents to a minimum. Three parallel MAX5037 converters deliver up to 180A of output current. To set the phase shift of the on-board PLL, leave PHASE unconnected for 90 of phase shift (2 paralleled converters), or connect PHASE to SGND for 60 of phase shift (3 converters in parallel). Designate one converter as master and the remaining converters as slaves. Connect the master and slave controllers in a daisychain configuration as shown in Figure 10. Connect CLKOUT from the master controller to CLKIN of the first slaved controller, and CLKOUT from the first slaved controller to CLKIN of the second slaved controller. Choose the appropriate phase shift for minimum ripple currents at the input and output capacitors. The master controller senses the output differential voltage through SENSE+ and SENSE- and generates the DIFF voltage. Disable the voltage sensing of the slaved controllers by leaving DIFF unconnected (floating). Figure 11 shows a detailed typical parallel application circuit using two MAX5037s. This circuit provides four phases at an input voltage of 12V and an output voltage range of 1.1V to 1.85V at 104A.
DIFF
PGOOD
DAC_OUT 8% OF DAC
10% OF DAC
CLP1
Overload Conditions
Average current-mode control has the ability to limit the average current sourced by the converter during a fault condition. When a fault condition occurs, the VEA output clamps to 0.9V with respect to the common-mode voltage (VCM = 0.6V) and is compared with the output of the current-sense amplifiers (CA1 and CA2) (see Figure 3). The current-sense amplifier's gain of 18 limits the maximum current in the inductor or sense resistor to ILIMIT = 50mV/RS.
+2.0V
CLP2 PHASE FAILURE DETECTION
Figure 9. Power-Good Generator 20 ______________________________________________________________________________________
VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller
Applications Information
Each MAX5037 circuit drives two 180 out-of-phase channels. Parallel two or three MAX5037 circuits to achieve four- or six-phase operation, respectively. Figure 1 shows the typical application circuit for twophase operation. The design criteria for a two-phase converter includes frequency selection, inductor value, input/output capacitance, switching MOSFETs, sense resistors, and the compensation network. Follow the same procedure for the four- and six-phase converter design, except for the input and output capacitance. The input and output capacitance requirement varies depending on the operating duty cycle. The examples discussed in this data sheet pertain to a typical VRM application with the following specifications: VIN = +12V VOUT = +1.1V to +1.85V IOUT(MAX) = 52A VCOREMAX = VID Programmed Output Voltage at No Load AVP (VOUT) = 120mV fSW = 250kHz Peak-to-Peak Inductor Current (IL) = 10A Table 2 shows a list of recommended external components (Figure 1) and Table 3 provides component supplier information.
MAX5037
Table 2. Component List
DESIGNATION C1, C2 C3-C11 C12, C13 C14, C15 C16-C25 C26-C30, C37 C31 C32, C34, C36 C33, C35, C43 C38 C39 C40, C41, C42 D1, D2 D3, D4 L1, L2 Q1, Q3 Q2, Q4 R1, R2 R3, R13 R4 R5, R6 R7 R8, R9 R11 R12 QTY 2 9 2 2 10 6 1 3 3 1 1 3 2 2 2 2 2 4 1 1 2 1 2 1 1 DESCRIPTION 47F, 16V X5R input-filter capacitors TDK C5750X5R1C476M 22F, 16V input-filter capacitors TDK C4532X5R1C226M 0.47F, 16V capacitors TDK C1608X5R1A474K 100F, 6.3V output-filter capacitors Murata GRM44-1X5R107K6.3 270F, 2V output-filter capacitors Panasonic EEFUE0D271R 10F, 6.3V output-filter capacitors TDK C2012X5R0J106M 4700pF, 16V X7R capacitor Vishay-Siliconix VJ0603Y471JXJ 470pF, 16V capacitors Murata GRM1885C1H471JAB01 0.01F, 50V X7R capacitors Murata GRM188R71H103KA01 4.7F, 16V X5R capacitor Murata GRM40-034X5R475k6.3 1.0F, 10V Y5V capacitor Murata GRM188F51A105 0.1F, 16V X7R capacitors Murata GRM188R71C104KA01 Schottky diodes ON-Semiconductor MBRS340T3 Schottky diodes ON-Semiconductor MBR0520LT1 0.6H, 27A inductors Panasonic ETQP1H0R6BFX Upper power MOSFETs Vishay-Siliconix Si7860DP Lower power MOSFETs Vishay-Siliconix Si7886DP Current-sense resistors, use two 2.70m resistors in parallel Panasonic ERJM1WSF2M7U 2.2 1% resistor 7.5k 1% resistor 1k 1% resistors 4.99k 1% resistor 37.4k 1% resistors 10k 1% resistor 10 1% resistor
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21
VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller MAX5037
CSN1 SENSE+ SENSEVCC PHASE DL1 DH1 LX1 CSP1 VIN
MAX5037
VCC CLKIN DH2 LX2 VIN IN DIFF EAN EAOUT PGND SGND CSP2 CSN2 CLKOUT DL2
VIN
CSN1 CLKIN CSP1 VIN DH1 LX1 PHASE DL1
VCC
IN
MAX5037
VIN DH2
DIFF
LX2 DL2
LOAD
EAN EAOUT PGND SGND CSP2 CSN2 CLKOUT
CSN1 CLKIN CSP1 VIN DH1 LX1 PHASE DL1
VCC
IN
MAX5037
DH2
VIN
DIFF
LX2 DL2
EAN EAOUT PGND SGND CSP2 CSN2 CLKOUT
TO OTHER MAX5037s
Figure 10. Parallel Configuration of Multiple MAX5037s 22 ______________________________________________________________________________________
VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller MAX5037
VIN = +12V VIN VCC C31 C32 R13 2.2 C1, C2 2 x 47F
C43
R12
R4
C42 0.1F 38 CLKIN 28 IN 11 10 17 16 SENSE- SENSE+ CSN1 CSP1 DH1
VIN C3-C7 5 x 22F 23 24 25 Q2 D1 Q1 L1 0.6H C12 0.47F R1 1.35m
8 OVPOUT 44 1 2 3 4 VCC 19 VID4
42 PLLCMP
LX1 VID3 DL1 VID2 VID1 VID0 EN VDD
BST1 VCC
22 27 C41 0.1F
D3
R3 28 C39 1F VIN
C38 4.7F D4
6 R7 12 13 R8 14
MAX5037 (MASTER)
OVPIN DIFF EAN DH2 EAOUT LX2
C40 0.1F
32 31 30
C8-C11 4 x 22F Q3 L2 0.6H C13 0.47F D2 R2 1.35m
R9
15
DL2 REG
Q4
R10
18
CNTR CLP1 7 CLP2 43 PGND 29 SGND 5, 20, 35 CLKOUT 36 PHASE PGOOD 41 9 CSN2 CSP2 40 39 BST2
34
R6 C36 C35
R5 C34 C33 VCC PGOOD
R11
R24
C14, C15, C44, C45 2 x 100F C70 VID0 VID1 DAC INPUTS VID2 VID3 VID4 R17 C61 0.1F 28 IN 38 CLKIN 11 10 17 16 SENSE- SENSE+ CSN1 CSP1 DH1 VID0 LX1 3 2 1 44 VID1 DL1 VID2 VID3 VID4 22 27 C64 0.1F C65 4.7F D8 C63 0.1F VIN DIFF EAN DH2 EAOUT LX2 R22 15 DL2 REG 32 31 30 C51-C54 4 x 22F Q7 L4 0.6H C56 0.47F D6 R15 1.35m 24 25 Q6 D5 C71 R24 2.2
C16-C25, C57-C60 2 x 270F
C26-C30, LOAD C37 6 x 10F
VOUT = +1.1V TO +1.85V AT 104A
R25 VIN 5 x 22F C46-C50 23 Q5 L3 0.6H C55 0.47F R14 1.35m
19 EN 4
42 PLLCMP
BST1 VCC
D7
R16 8 OVPOUT VDD 28 C62 1F
R20
6 12 13
MAX5037 (SLAVE)
OVPIN
R21
14
Q8
R23
18
CNTR CLP1 7 CLP2 43 PGND 29 SGND PHASE PGOOD CSN2 CSP2 5, 20, 35 41 9 40 39 BST2
34
R19 C66 C67
R18 C69 C68 VCC
Figure 11. Four-Phase Parallel Application Circuit (VIN = +12V, VOUT = +1.1V to +1.85V at 104A) ______________________________________________________________________________________ 23
VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller MAX5037
Table 3. Component Suppliers
SUPPLIER Murata ON Semiconductor Panasonic TDK Vishay-Siliconix PHONE 770-436-1300 602-244-6600 714-373-7939 847-803-6100 1-800-551-6933 FAX 770-436-3030 602-244-3345 714-373-7183 847-390-4405 619-474-8920 WEBSITE www.murata.com www.on-semi.com www.panasonic.com www.tcs.tdk.com www.vishay.com
Number of Phases
Selecting the number of phases for a voltage regulator depends mainly on the ratio of input-to-output voltage (operating duty cycle). Optimum output-ripple cancellation depends on the right combination of operating duty cycle and the number of phases. Use the following equation as a starting point to choose the number of phases: (7) NPH K/D where K = 1, 2, or 3 and the duty cycle D = VOUT/VIN. Choose K to make NPH an integer number. For example, converting VIN = +12V to VOUT = +1.75V yields better ripple cancellation in the six-phase converter than in the four-phase converter. Ensure that the output load justifies the greater number of components for multiphase conversion. Generally, limiting the maximum output current to 25A per phase yields the most costeffective solution. The maximum ripple cancellation occurs when NPH = K/D. Single-phase conversion requires greater size and power dissipation for external components such as the switching MOSFETs and the inductor. Multiphase conversion eliminates the heatsink by distributing the power dissipation in the external components. The multiple phases operating at given phase shifts effectively increase the switching frequency seen by the input/output capacitors, reducing the input/output capacitance requirement for the same ripple performance. The lower inductance value improves the large-signal response of the converter during a transient load at the output. Consider all these issues when determining the number of phases necessary for the voltage regulator application.
Adaptive Voltage-Positioning Design Procedure
The following steps outline the procedure for setting the adaptive voltage positioning: 1) Choose the voltage-error amplifier input (EAN) resistor RIN > 5k. 2) Determine a reasonable amount of excursion from the desired output voltage that the system can tolerate and use as an estimate for the voltage-positioning window, VOUT (see Figures 5 and 7). 3) Calculate R F from equations 22 and 23. Use Equation 3 to verify that VOUT remains within tolerable limits. 4) Calculate the centering resistor, R CNTR , from Equation 5. RCNTR sets the center of the adaptive voltage positioning such that at 1/2 full-load current, the output voltage is the desired VID programmed output voltage (Figure 5). Do not use values less than 24k for RCNTR. 5) Choose the regulation resistor, RREG, to have the same value as the feedback resistor, RF (RREG = RF). RREG maintains the adaptive voltage-positioning window at all VID output voltage settings. Do not use values less than 37k for RREG.
Inductor Selection
The switching frequency per phase, peak-to-peak ripple current in each phase, and allowable ripple at the output determine the inductance value. Selecting higher switching frequencies reduces the inductance requirement, but at the cost of lower efficiency. The charge/discharge cycle of the gate and drain capacitances in the switching MOSFETs create switching losses. The situation worsens at higher input voltages, since switching losses are proportional to the square of input voltage. Use 500kHz per phase for VIN = +5V, 250kHz or less per phase for VIN > +12V.
24
______________________________________________________________________________________
VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller
Although lower switching frequencies per phase increase the peak-to-peak inductor ripple current (IL), the ripple cancellation in the multiphase topology reduces the input and output capacitor RMS ripple current. Use the following equation to determine the minimum inductance value:
Switching MOSFETs
When choosing a MOSFET for voltage regulators, consider the total gate charge, RDS(ON), power dissipation, and package thermal impedance. The product of the gate charge and on-resistance of the MOSFET is a figure of merit, with a lower number signifying better performance. Choose MOSFETs optimized for high-frequency switching applications. The average gate-drive current from the MAX5037 output is proportional to the total capacitance it drives from DH1, DH2, DL1, and DL2. The power dissipated in the MAX5037 is proportional to the input voltage and the average drive current. See the VIN, VCC, and VDD section to determine the maximum total gate charge allowed from all the driver outputs together. The gate charge and drain capacitance (CV2) loss, the cross-conduction loss in the upper MOSFET due to finite rise/fall time, and the I2R loss due to RMS current in the MOSFET R DS(ON) account for the total losses in the MOSFET. Estimate the power loss (PDMOS_) in the highside and low-side MOSFETs using following equations: PDMOS-HI = (QG x VDD x fSW ) + (11)
MAX5037
LMIN =
(VINMAX
VIN x fSW x IL
- VOUT ) x VOUT
(8)
Choose IL equal to about 40% of the output current per phase. Since IL affects the output ripple voltage, the inductance value may need minor adjustment after choosing the output capacitors for full-rated efficiency. Choose inductors from the standard high-current, surface-mount inductor series available from various manufacturers. Particular applications may require custom-made inductors. Use high-frequency core material for custom inductors. High IL causes large peak-topeak flux excursion increasing the core losses at higher frequencies. The high-frequency operation coupled with high IL, reduces the required minimum inductance making possible even the use of planar inductors. The advantages of using planar magnetics include low-profile design, excellent current-sharing between phases due to the tight control of parasitics, and low cost. For example, calculate the minimum inductance at VIN(MAX) = +13.2V, VOUT = +1.75V, IL = 10A, and fSW = 250kHz:
VIN x IOUT x (tR + tF ) x fSW 2 + 1.4RDS(ON) x I RMS-HI 4
where QG, RDS(ON), tR, and tF are the upper-switching MOSFET's total gate charge, on-resistance at +25C, rise time, and fall time, respectively.
LMIN =
(13.2 - 1.75) x 1.75 = 0.6H
13.2 x 250k x 10
IRMS-HI =
(I
D 2 2 DC + I PK + IDC x IPK x 3
)
(12)
(9) The MAX5037 average current-mode control feature limits the maximum peak-inductor current which prevents the inductor from saturating. Choose an inductor with a saturating current greater than the worst-case peak inductor current. Use the following equation to determine the worst-case inductor current for each phase: IL _ PEAK = 0.051 I +L RSENSE 2
where D = V OUT /V IN , I DC = (I OUT - I L )/2 and I PK = (IOUT + IL)/2 PDMOS-LO = (QG x VDD x fSW ) +
2 2xC 2 OSS x VIN x fSW + 1.4R DS(ON) x I RMS-LO 3
(13)
where RSENSE is the sense resistor in each phase. (10)
IRMS-LO =
(I
1- D 2 2 DC + I PK + IDC x IPK x 3
)
(
)
(14)
______________________________________________________________________________________
25
VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller MAX5037
For example, from the typical VRM specifications in the Applications Information section with VOUT = +1.75V, the high-side and low-side MOSFET RMS currents are 9.9A and 24.1A, respectively. Ensure that the thermal impedance of the MOSFET package keeps the junction temperature at least +25C below the absolute maximum rating. Use the following equation to calculate maximum junction temperature: TJ = PDMOS x J-A + TA (15)
Output Capacitors
The worst-case peak-to-peak and capacitor RMS ripple current, the allowable peak-to-peak output ripple voltage, and the maximum deviation of the output voltage during step loads determine the capacitance and the ESR requirements for the output capacitors. In multiphase converter design, the ripple currents from the individual phases cancel each other and lower the ripple current. The degree of ripple cancellation depends on the operating duty cycle and the number of phases. Choose the right equation from Table 4 to calculate the peak-to-peak output ripple for a given duty cycle of two-, four-, and six-phase converters. The maximum ripple cancellation occurs when NPH = K / D. The allowable deviation of the output voltage during the fast-transient load dictates the output capacitance and ESR. The output capacitors supply the load step until the controller responds with a greater duty cycle. The response time (tRESPONSE) depends on the closed-loop bandwidth of the converter. The resistive drop across the capacitor ESR and capacitor discharge causes a voltage drop during a step load. Use a combination of SP polymer and ceramic capacitors for better transient load and ripple/noise performance.
Input Capacitors
The discontinuous input-current waveform of the buck converter causes large ripple currents in the input capacitor. The switching frequency, peak inductor current, and the allowable peak-to-peak voltage ripple reflected back to the source dictate the capacitance requirement. Increasing the number of phases increases the effective switching frequency and lowers the peak-to-average current ratio, yielding lower input capacitance requirement. The input ripple is comprised of VQ (caused by the capacitor discharge) and VESR (caused by the ESR of the capacitor). Use low-ESR ceramic capacitors with high ripple-current capability at the input. Assume the contributions from the ESR and capacitor discharge are equal to 30% and 70%, respectively. Calculate the input capacitance and ESR required for a specified ripple using the following equation: ESRIN =
Table 4. Peak-to-Peak Output Ripple Current Calculations
NUMBER OF PHASES (N) 2 DUTY CYCLE (D) < 50% EQUATION FOR IP-P
IOUT IL + N 2
(VESR )
(16)
V (1 - 2D) I = O L x fSW I =
IOUT x D(1 - D) CIN = N VQ x fSW
(17)
2
> 50%
(VIN - VO )(2D - 1)
L x fSW V (1- 4D) I = O L x fSW
where IOUT is the total output current of the multiphase converter and N is the number of phases. For example, at V OUT = 1.75V, the ESR and input capacitance are calculated for the input peak-to-peak ripple of 100mV or less yielding an ESR and capacitance value of 1m and 200F.
4
0 to 25%
4
25 to 50%
V (1 - 2D)(4D - 1) I = O 2 x D x L x fSW V (2D - 1)(3 - 4D) I = O D x L x fSW V (1- 6D) I = O L x fSW
4
> 50%
6
< 17%
26
______________________________________________________________________________________
VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller
Keep the maximum output voltage deviation less than or equal to the adaptive voltage-positioning window (VOUT). Assume 50% contribution each from the output capacitance discharge and the ESR drop. Use the following equations to calculate the required ESR and capacitance value: ESROUT = VESR ISTEP (18) RF = IOUT x RIN N x GC x VOUT (22) A resistive feedback around the VEA provides the best possible response, since there are no capacitors to charge and discharge during large-signal excursions. The required amount of adaptive voltage positioning (VOUT) determines the VEA gain. Use the following equation to calculate the value for RF when using adaptive voltage positioning:
MAX5037
I xt COUT = STEP RESPONSE VQ
(19)
GC =
0.05 RS
(23)
where I STEP is the load step and t RESPONSE is the response time of the controller. Controller response time depends on the control-loop bandwidth.
where GC is the current-source gain and N is the number of phases. When designing the current-control loop ensure that the inductor downslope (when it becomes an upslope at the CEA output) does not exceed the ramp slope. This is a necessary condition to avoid sub-harmonic oscillations similar to those in peak current-mode control with insufficient slope compensation. Use the following equation to calculate the resistor RCF: RCF 2 x fSW x L x 102 VOUT x RSENSE (24)
Current Limit
The average current-mode control technique of the MAX5037 accurately limits the maximum output current per phase. The MAX5037 senses the voltage across the sense resistor and limits the peak inductor current (IL-PK) accordingly. The ON cycle terminates when the current-sense voltage reaches 45mV (min). Use the following equation to calculate maximum current-sense resistor value: 0.045 RSENSE = IOUT N PDR = 2.5 x 10-3 RSENSE (20)
For example, the maximum RCF is 12k for RSENSE = 1.35m. (21) CCF provides a low-frequency pole while RCF provides a midband zero. Place a zero at fZ to obtain a phase bump at the crossover frequency. Place a high-frequency pole (fP) at least a decade away from the crossover frequency to achieve maximum phase margin. Use the following equations to calculate CCF and CCFF: CCF = 1 2 x x fZ x RCF
where PDR is the power dissipation in sense resistors. Select 5% lower value of RSENSE to compensate for any parasitics associated with the PC board. Also, select a non-inductive resistor with the appropriate wattage rating.
Compensation
The main control loop consists of an inner current loop and an outer voltage loop. The MAX5037 uses an average current-mode control scheme to regulate the output voltage (Figure 3). IPHASE1 and IPHASE2 are the inner average current loops. The VEA output provides the controlling voltage for these current sources. The inner current loop absorbs the inductor pole reducing the order of the outer voltage loop to that of a single-pole system.
(25)
CCFF =
1 2 x x fP x RCF
(26)
______________________________________________________________________________________
27
VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller MAX5037
PC Board Layout
Use the following guidelines to layout the switching voltage regulator. 1) Place the V IN , V CC, and V DD bypass capacitors close to the MAX5037. 2) Minimize the high-current loops from the input capacitor, upper switching MOSFET, inductor, and output capacitor back to the input capacitor negative terminal. 3) Keep short the current loop from the lower switching MOSFET, inductor, output capacitor, and return to the source of the lower MOSFET. 4) Place the Schottky diodes close to the lower MOSFETs and on the same side of the PC board. 5) Keep the SGND and PGND isolated and connect them at one single point close to the negative terminal of the input filter capacitor. 6) Run the current-sense lines CS+ and CS- very close to each other to minimize the loop area. Similarly, run the remote voltage sense lines SENSE+ and SENSE- close to each other. Do not cross these critical signal lines through power circuitry. Sense the current right at the pads of current-sense resistors. 7) Avoid long traces between the VDD bypass capacitors, driver output of the MAX5037, MOSFET gates and PGND pin. Minimize the loop formed by the VDD bypass capacitors, bootstrap diode, bootstrap capacitor, MAX5037, and upper MOSFET gate. 8) Place the bank of output capacitors close to the load. 9) Distribute the power components evenly across the board for proper heat dissipation. 10) Provide enough copper area at and around the switching MOSFETs, inductor, and sense resistors to aid in thermal dissipation. 11) Use at least 4oz copper to keep the trace inductance and resistance to a minimum. Thin copper PC boards can compromise efficiency since high currents are involved in the application. Also, thicker copper conducts heat more effectively, thereby reducing thermal impedance.
Pin Configuration
PLLCMP CLKOUT PHASE CLKIN SGND N.C. CSN2 CSP2
CLP2
44 43 42 41 40 39 38 37 36 35 34 VID3 1 VID2 2 VID1 3 VID0 4 SGND 5 OVPIN 6 CLP1 7 OVPOUT 8 PGOOD 9 SENSE+ 10 SENSE- 11 12 13 14 15 16 17 18 19 20 21 22 DIFF EAN REG EN CSN1 CNTR CSP1 EAEOUT SGND BST1 33 N.C 32 DH2 31 LX2 30 DL2 29 PGND
BST2 28 IN 27 VCC 26 VDD 25 DL1 24 LX1 23 DH1
VID4
MAX5037
MQFP/QFN*
*CONNECT THE QFN EXPOSED PAD TO SGND GROUND PLANE
Chip Information
TRANSISTOR COUNT: 5431 PROCESS: BiCMOS
28
______________________________________________________________________________________
N.C.
VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX5037
______________________________________________________________________________________
MQFP44.EPS
29
VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller MAX5037
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
D2 D D/2 k
C L
b D2/2
E/2 E2/2 (NE-1) X e
C L
E
E2
k L DETAIL A e (ND-1) X e
C L
C L
L
L
e
e
A1
A2
A
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 32, 44, 48L QFN THIN, 7x7x0.8 mm
DOCUMENT CONTROL NO. REV.
APPROVAL
21-0144
1 2
B
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
** NOTE: T4877-1 IS A CUSTOM 48L PKG. WITH 4 LEADS DEPOPULATED. TOTAL NUMBER OF LEADS ARE 44.
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 32, 44, 48L QFN THIN, 7x7x0.8 mm
DOCUMENT CONTROL NO. REV.
APPROVAL
21-0144
2 2
B
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
30 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
32, 44, 48L QFN .EPS

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